This invention relates to a variable delay circuit suitable for use in an information processor such as a computer, and a clock signal supply unit using the same variable delay circuit.
Examples of the clock signal supply unit are disclosed in U.S. Pat. No. 5,184,027 issued on Feb. 2, 1993 and U.S. Pat. No. 5,043,596 issued on Aug. 27, 1991, both assigned to Hitachi Ltd., as is as the present patent application; on JP-A-2-168308, filed on Sep. 13, 1989 by Hitachi Ltd.
In the clock signal supply units disclosed in these publications, a source signal and a reference signal from a clock generator are supplied to destinations which require clock signals. Each destination has a variable delay circuit and uses this variable delay circuit to adjust the source clock signal so as to be in phase with the reference signal.
In order for a clock signal having high phase accuracy to be available for the destinations, it is required to raise the phase accuracy of the reference signal and compare the phases of the clock signal and the reference signal with high accuracy. In the above-mentioned publications, there are revealed reference signal supply circuits and methods as well as phase comparator circuits and methods which meet the above-mentioned requirement.
In JP-A-63-106816, filed on Oct. 24, 1986 by NEC Corporation, there is shown a method for adjusting the phase of the clock signal by a variable delay circuit. In this laid-open publication, no consideration has been made of the automatic phase adjustment for the clock signal, nor the variable range and the resolution in the adjustment of the variable delay circuit.
In JP-A-2-254809, filed on Mar. 28, 1989 by Mitsubishi Electric Corporation, there is shown a method for controlling a delay time by connecting a plurality of transfer gates in the clock signal transmission line and controlling the number of the conducting transfer gates. In this method disclosed in this laid-open publication, if one wishes to increase the phase adjusting range, it is necessary to increase the number of transfer gates directly connected to the clock signal transmission line, which results in an increase in the minimum delay time.
In the phase adjusting device in the conventional clock signal supply unit, immediately after the phase adjustment a clock signal with high phase accuracy can be obtained, but thereafter if the temperature of the device changes, the phase of the clock signal changes, too. Therefore, unless this device is used in a system subject to a limited range of temperature change in steady state (an expensive system equipped with a water cooling device, for example), the phase accuracy deteriorates if there is no means that follows up changes in temperature in controlling the delay time.
JP-A-2-168308 discloses an example of a variable delay circuit which can follow changes in temperature. However, if one wishes to increase the follow-up range of temperature change without coarsening the resolution (a difference between a delay time that occurs when a control signal is applied and a delay time that occurs when this control signal is varied by one step) in delay time control, in this variable delay circuit, it is necessary to increase the stages of selectors, which results in an increase of the minimum delay time (a delay time that is produced by applying such a control signal is applied so as to minimize the delay time of the variable delay circuit). A result of this is an increase in the range of phase change in relation to a given change in temperature. In order to correct this, a wider follow-up range is required. In consequence, when the technique disclosed in JP-A-2-168308 is used to follow up temperature changes, there is no other choice but to coarsen the resolution in phase control to some extent.
In the technique disclosed in JP-A-2-168308, to prevent a spike-like noise from occurring in the clock signal output, flip-flops are used to inhibit the switch-over timing of the selector from being superposed on a rise or a fall of the clock signal. However, for such flip-flops, a high-speed circuit is required which can follow up the frequency of the clock signal.
With a variable delay circuit used in the conventional clock phase adjusting device, increasing the variable range of the variable delay circuit requires an increase in the stages of selectors, resulting in an increase in the minimum delay time. The skew increases' which is attributable to variations in the manufacture of semiconductor devices constituting this variable delay circuit. To correct this, a greater variable range is required. Particularly in a CMOS circuit widely used in a less expensive system, this problem is conspicuous because of the great variations in delay time.